Improving the error floor performance of LDPC codes

Low-density parity-check codes (LDPC) have become one of the most popular error-correcting code families in recent years due to their high error correction performance and easy implementation. They became one of the biggest candidates to become a standard in the next-generation wireless communication systems. In particular, quasi-cyclic (QC)-LDPC codes have been chosen as the standard codes for 5G mobile broadband. However, at high signal-to-noise ratio values, the error-correcting performance of LDPC codes decreases due to harmful structures called trapping sets. Designing an LDPC code with few or no harmful structures is one of the popular topics in recent years. In this thesis, firstly, an adaptive linear decoder is designed that can decode LDPC codes with high error-correcting performance. Then, simulated annealing algorithms are proposed to reduce the number of cycles and trapping sets. Finally, new QC-LDPC codes have been designed with the proposed algorithm. In terms of trapping sets distribution, the best short-length QC-LDPC code constructions in the literature have been achieved.