Avoiding register file inefficiency in terms of power and reliability

Processor register file is one of the most active structures of the processor datapath, interacting with many components in several pipeline stages. However register file has not been well-optimized in terms of energy and data redundancy. In our studies, our goal is to optimize its energy inefficency in the first part and to exploit the inefficient register redundancy for better reliability in the second part. In modern architectures the register file is one of the most energy consuming and frequently used components of the processor. Therefore, reducing the register file power dissipation is critical. In this thesis, we propose schemes that reduce the energy dissipation of the register file by not writing the bits that are not changed. Our schemes rely on the observation that on the average only 10% of the register bits are changed by the instructions at each operation. In this study, we propose a combination of architectural and circuit level techniques that exploit this inefficiency for the register file's write power reduction using an update-based scheme. We show that for a 64-bit datapath it is possible to reduce the energy dissipation of the register file up to 24.85% for individual benchmark programs and by 20.59% on the average across all simulated benchmarks with a negligible performance compromise. Soft errors caused by the cosmic particles or the radiation from the packaging material of the integrated circuits are an increasingly important design problem. With the shrinking feature sizes, the datapath components of the out-of-order superscalar pipeline are becoming more prone to soft errors. Being the major data holding component in contemporary microprocessors, the register file has been an important part of the processor on which researchers offered many different schemes to protect against soft errors. We start with the observation that many of the stored values inside the register file have very small Hamming distances when compared to each other. After showing this analysis results we propose a soft error correction scheme that makes use of the presence of multiple register values that have zero Hamming distance from each other. We use this already available redundancy along with parity protection to achieve error correction for many of the stored values. We also extend the coverage of our scheme to offer coverage for values that are small hamming distances apart from each other. Our results show that, by employing schemes that make use of the already available copies of the values inside the register file, it is possible to protect 20.5% of the registers from soft errors with an additional power consumption of 2.8%. If we include the extension which duplicates active registers to idle registers to increase redundancy, protection coverage increases to 44.1% of the register file, with an increased power dissipation of 18.9%. Instead of duplicating, with negligible power overhead, it is possible to extend the coverage to 39.8% by exploiting the values that differ only a few bits in their least significant byte.