Exploiting virtual addresses for achieving fault tolerance in microprocessors

In this thesis a novel method to protect a system against faults resulting from softerrors occuring in the virtual address storing structures such as translation buffers,physical register file and the program counter. The work is motivated by showinghow soft errors impact the structures that store virtual addresses. A solution isproposed by employing linear block encoding methods to be used as a virtualaddressing scheme at link time.Using the encoding scheme to assign virtualpage numbers for virtual addresses, it is shown that the system can tolerate softerrors using software with the help of the discussed decoding techniques appliedto the page fault handler. Hardware solutions can also be applied at the programcounter and the physical regiser file providing ECC protection without the burdenof using circuit level encoding.The main contribution of this thesis is the decreasing of AVF for data translationbuffer by 42.5%, instruction translation buffer by 40.3%, program counter by69.2% and physical register file by 33,3%.