A new approach to set-based dynamic cache partitioning on chip multiprocessors

Modern processors contain multiple cores which enables them to concurrently execute multiple applications on a single chip in parallel. As the number of cores on a chip increases, the pressure on the memory system to sustain the memory requirements of all the concurrently executing threads increases. Worst of all, today's processor architectures bring many cores next to each other and hope that the applications running on these cores are going to share the last level cache without any problem. As a result, applications, which have no clue that there are other neighbors competing for the same resources, think that each of them has a dedicated cache and start a competition of stealing cache lines from each other without even knowing it. In such cases, an application with a large memory foot print may spoil the cache and, suddenly, this may render the last level cache in a position bringing more harm (drop of performance, unnecessary power and energy dissipation) than any good. So, one of the keys to obtaining high performance from multicore architectures is to manage the Last Level Cache (LLC) efficiently. This new approach calculates the efficiency of each application with the help of application-based runtime statistics collected by hardware counters. According to these statistics, we classify the threads that are executed concurrently. At the end, we try assigning Last Level Cache partitions to running threads considering their instant behavior detected by the Classifier circuit. Consequently, the system aims to improve the performance of individual applications and total system throughput by giving more cache sets to the applications with more throughput potentials when they receive more cache resources. The secondary aim of the proposed method is its scalable design for many-core architectures.