New approaches to optimization algorithms used in circuit and system level of analog design automation

This thesis presents different simulation-based analog circuit synthesis methodologies, and synthesis examples that were performed to validate the usefulness of the methodologies. It also presents the integration of circuit synthesizer with system level. Simulation-based approach is preferred so that the synthesizer, SACSES, is implemented with HSPICE. Two different circuit synthesis methodologies that manipulate device size indirectly by using modified ES algorithm are proposed. The first one is based on the inversion coefficient (IC) as a key design parameter and the equation of the EKV MOSFET Model. The second one is based on DC operating points and lookup-tables used for translating DC operating points into transistor dimensions. A hierarchical synthesis structure is proposed for integrating SACSES with system level synthesis. The hierarchical scheme eliminates the need for extra tools to link levels.