Hardware implementation of random number generators

In this thesis, one of the symmetric cryptographic algorithms known as the Trivium algorithm is implemented by making use of its Field Programmable Gate Array (FPGA). After introducing random number generation and cryptographic concepts briefly, we focus on the design structures of stream ciphers. After using the VHDL (Very High Speed Integrated Curriculent Hardware Description Language) programming language in order to obtain some simulation results, a 128-bit random number is generated as a result of the 80-bit key input. Later, the test criteria have been mentioned briefly and the produced 128-bit random values are subjected to these criteria. Finally, these randomly generated numbers are implemented in the FPGA and corresponding test results are discussed.