Set-based dynamic cache partitioning on chip multiprocessors

Today, most of the chip multiprocessor architectures utilize a shared second level cache to reduce the off-chip memory delay. However, benefit from such a cache may be very limited due to cache conflicts caused by applications running in parallel. The alternative approach of having a private second level cache dedicated to each core is also problematic, since there are always applications with large memory footprints or shared address space requirements. In the literature, there are numerous studies that try to partition the second level cache. These studies generally focus on dedicating an appropriate number of ways and policies to each core according to the runtime memory requirements of applications. On the contrast, this study proposes a mechanism to dynamically partition the cache based on sets. In this mechanism, the resizing decisions for each logical partition are made according to the runtime statistics collected by the hardware at periodic time intervals. Since the mechanism focuses on cache sets rather than cache ways, the resizing of the cache partitions can be done in a finer-grain, any cache policies can be freely chosen and, the additional complexity requirements can be kept at minimum compared to other schemes. When compared to the shared baseline cache configuration, the performance (throughput) gain in workloads containing solely memory-intensive applications is as much as 9 per cent, on the average. For hybrid workloads that run memory- and computation-intensive applications together, the performance is improved by more than 15 per cent on the average across all simulated application mixtures.