Soc tabanlı donanım hızlandırmalarında hls performansını yükseltme

Modern large-scale computing algorithms require huge amount of computational power. In adapting to increasing computation demands, FPGA-based SoC platforms provide an alternative to traditional CPU or GPU units, which suffer from thermal problems, power issues, etc. However, design flow for FPGA based development may be hard and time-consuming for an average software engineer who has limited knowledge about hardware design. A new approach in FPGA-based system development without the need for a hardware engineer is to program the FPGA using high level synthesis (HLS) tools that resembles C-based languages. Commercial HLS tools provide different kinds of automatic and user-defined optimizations for loop kernels such as pipelining, loop unrolling, etc. However, these techniques only provide instruction-level pipelining and reduce loop enter and exit overheads to decrease execution time of algorithms running on programmable logic (PL) side of SoC systems. The limited approach of HLS for loop kernels can be extended by adding front-end operations to input code of HLS tools. In this thesis, we propose a semi-autonomous polyhedral analysis and optimization-based methodology in order to enable course grained parallelization on nested loop structures to increase final design efficiency. Xilinx Zynq SoC FPGA platform and Vivado Design Suite Tool are used in order to show how our proposed approach could be applied.