Verysimplecpu and synthesis of customized multi-core microcontrollers

This dissertation proposes the design and implementation of customizable multi-core microcontrollers (MCUs) on field programmable gate arrays (FPGAs) for low-cost embedded systems applications. Our proposed "Multi-Core Microcontroller Synthesis from C" (or shortly MC2SC) methodology provides a design flow that takes C programs as input, and then compiles, analyzes, profiles them and finally generates application-specific MCUs accordingly. Each MCU can run its own set of specific tasks in parallel and without tight scheduling constraints that are imposed by the other tasks within an application. In addition, each MCU can also have its own set of peripherals like GPIO, I2C, SPI, etc. For this purpose, we designed a simple, customizable, and Turing-complete soft processor named VerySimpleCPU (VSCPU) and extended its base architecture with various features including two different ISAs, memory-mapped I/O support, shared memory, etc. We also developed a toolchain for VSCPU that includes a C compiler, an application profiler, a worst-case execution time (WCET) analyzer, an assembler, and a cycle-accurate instruction set simulator. Furthermore, we developed a hardware generator that takes the system profile of the application, which is generated by the application profiler, and then generates the corresponding RTL design for the application. We evaluated and tested our proposed MC2SC methodology in five different use cases and showed that it can be used as an alternative to other hardware/software (HW/SW) co-design and co-synthesis techniques. VSCPU also proved useful in computer architecture education. Therefore this dissertation also includes a discussion of critical topics in computer architecture education. We surveyed 25 textbooks on computer architecture and 38 papers on computer architecture education from the perspective of 18 critical topics. We also introduced our own approach to teach computer architecture based on VSCPU and share our results.