Modeling soft errors for data caches in chip multiprocessor systems

Recently we have been witnessing a dramatic shift in processor design from a very powerful, more complex, and more-power-hungry single superscalar cores running at very high clock speeds to chip multiprocessor (CMP) system with multiple cores in the same chip with each less powerful, simpler, consuming less power, and operating at lower clock speeds. The force behind this shift is that we almost approach the physical hard limits (designing finer transistors and controlling power consumption are becoming more challenging) and that increasing issue rate beyond four brings little additional benefit in performance since most of applications do not support larger instruction level parallelism (ILP). Also, multi-core demanding multithreaded workloads such as web servers, databases, and parallel scientific codes have become more widespread.On the other hand, radiation-induced soft errors introduced by particle strikes such as neutron particles in cosmic rays and alpha particles from packaging materials pose a significant problem for microprocessors to run in a reliable manner. In this study, we try to model the soft errors in first level data caches in a CMP system based on which we calculate the architectural vulnerable factor (AVF) for the first level data cache system. The AVF for a component is described as the probability with which a fault in this component can reveal itself in the final output of the program. Although there are a numerous number of previous studies related to the calculation of AVF and modelling the soft errors for different components in single core processors, there is dearth of such studies for CMPs. Our model models the soft error generation and propagation as well. We divide up the critical errors into different categories, based on which we calculate the AVF. Our experimental results show that the soft errors spreading from private L1 caches into the shared L2 cache is a major contributor of the overall AVF.