FPGA-based multi-channel digitizer design

With recent technological advancements over the past few years, the utilization of subsystems operating in a decentralized manner in various electronic hardware systems has increased. Particularly for measurement processes requiring high speeds, hardware systems differ from visualization and interface systems that operate at lower speeds, providing diversity. However, in these systems, data transfer between units operating at different speeds is a crucial requirement. Establishing a buffer between units operating at different speeds is considered the most effective way for accurate and reliable data transmission. The purpose of this thesis is to design a low-cost digital converter on FPGA to perform measurements and facilitate communication with minimal data loss between a digitizer and serial communication units operating at different clock speeds. Within the scope of the thesis, FIFO buffer architectures on FPGA have been examined, and a suitable structure has been established. Additionally, hardware has been selected considering both low cost and sufficient ADC speed. As a result, measurements in the range of 0-3.3V were obtained using an 8-channel 16-bit ADC, and the data were transmitted to a visualization device via UART in 20 ms intervals. FIFO was also employed to prevent synchronization issues that may arise from different clock speeds between ADC and UART.