Using Euler algorithm on FPGA Van der Pol oscillator of 32-bit IEEE 754-1985 and IQ-Math number standard design and realization

In recent years, chaos or chaotic engineering applications have shown widespread applicability in many areas of engineering. In the literature, one of the most important structures of chaotic engineering studies is the chaos signal generator. The operating frequency and other characteristics of the chaotic signal generator are very important in chaotic engineering applications. Many chaotic systems have been proposed in the literature such as 2-dimensional, 3-dimensional, 4-dimensional and 5-dimensional with different dynamic properties. The chaotic system to be preferred according to the platform used or designed varies. In this thesis, the chaotic Van der Pol system is designed to work on FPGA chip for real time chaos applications. In the present study, the chaotic Van der Pol system is modeled numerically using Euler algorithm ODE (Ordinary Differential Equation) solver on Matlab. The numerical structure of the chaotic Van der Pol oscillator designed on Matlab is taken as reference for the design of the chaotic Van der Pol oscillator unit on the real-time FPGA chip. The Chaotic Van der Pol system is encoded in the Multi-Speed Integrated Circuits Hardware Definition Language (VHDL) using the 32-bit IEEE-754-1985 floating-point number standard and the 32-bit (16I-16Q) IQ-Math fixed-point number standard. The designed chaotic Van der Pol system was synthesized in Xilinx ISE Project Navigator program and implemented on Xilinx VIRTEX-6 chip family, XC6VLX75T device, FF784 package. The operating frequency of the FPGA-based chaotic Van der Pol oscillator unit according to the 32-bit IQ-Math number standard is 498,728 MHz and the maximum operating frequency of the Van der Pol oscillator unit according to the 32-bit IEEE 754-1985 number standard is 483,074 MHz. Therefore, the Van Der Pol oscillator unit based on 32-bit IQ-Math fixed point number standard based on the 32-bit IEEE-754-1985 floating point number standard-based Van Der Pol oscillator unit designed on FPGA using the Euler algorithm has a higher operating frequency and lower source use. In addition, chip statistics obtained from the designs of FPGA based Van der Pol oscillator according to IEEE 754-1985 number standard and 32-bit IQ-Math number standard are presented.