Mixed mode hardware design of a general purposed artificial neural network

Artificial Neural Networks came on the scene as a result of the studies on artificial simulation of the human brain?s working system. Artificial Neural Networks, that can mathematically signifying the working principle of neurons with superior operation capability, are presenting the advantages of biological neurons to the service of science and technology in software and hardware platform. The human brain, differently from todays digital computers, has the capability of high speed processing as it has a dense parallel structure. Artificial neural network models require a lot of computing time to be simulated on a computer resulting a great difficulty to investigate the behavior of the large networks. Development of advanced microelectronic and Very Large Scale Integration (VLSI) technology for massivley parallel processing paradigms has been the main focus of actice research by many scientists and neural network researchers. Studies on circuitry designing of a number of artificial neuron models, network topologies and learning algorithms have been done with different hardware technics. In this study, the designed integrated circuitry of a general purposed artificial neural network, which is capable of making automatic decision boundaries depending on the data distribution, is realized. Designed circuitry of Conic Section Function Neural Networks (CSFNN) combine the propagation rules of Radial Basis Functions (RBF) and Multilayer Perceptrons (MLP) on a single neural network with a unique propagation rule. Hyperplanar decision boundaries of MLP and hyperspherical decision boundaries of MLP are special cases of CSFNN. Except from these decision boundaries, intermadiate types of decision boundaries such as hyperbolic, parabolic and elliptic planes can be obtained with CSFNN. CSFNN, capable of making open and closed decision regions, realizes the local and global mapping alone, depending on the data distribution. This ability of CSFNN is gained on desinged integrated circuit. In the integrated circuitry, designed by mixed mode hardware techniques, feed forward processing of neural network is realised with current mode analog circuitry. Classification performance of the integrated circuit has been increased by using Chip-in-the-loop learning technique during the training process. In general purposed designed integrated circuit, user is allowed to adjust the size of the CSFNN. Programmability of the integrated circuitry of CSFNN, provide flexibility to be applicable in different problems. The classification performance of integrated circuitry is tested with iris plant clasification and signature recognition problems. The simulations, the layout of integrated circuitry and post simulations have been realized at Cadence design tool using AMIS 0.5?m model parametres and design rules. Parameter variation curves have been obtained in order to investigate the effects of changing environment temprature and power supply voltage on circuit performance. Keywords. Conic section function neural network, mixed-mode hardware, neural network integrated circuits, chip-in-the-loop training technique.