FPGA design and implementation of a real-time stereo vision system

Stereo correspondence is the problem of discovering the closest possible match between two images captured simultaneously from cameras in different spatial locations. The differences between the positions of the matching points are the stereo disparity value. Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye.This thesis describes the implementation and design of the real-time stereo vision system on Field Programmable Gate Arrays (FPGA). Stereo vision is the most important in the field of depth measuring in 3D feature detection.This work proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices.