Low power techniques for superscalar microprocessors

University :TOBB Economics and Technology UniversityInstitute :Institute of Natural and Applied SciencesScience Programme :Electrical and Electronics EngineeringSupervisor :Associate Professor Onder EfeDegree Awarded and Date :M.S. - June 2007Y. Sinan HANAYLOW POWER TECHNIQUES FOR SUPERSCALAR MICROPROCESSORSABSTRACTThis thesis proposes and analyzes some techniques aiming at reducing powerdissipation of superscalar microprocessors. Nowadays, the drive toward fastermicroprocessors continues while requiring low power dissipation at the same time.The Moore?s law states that the number of transistors that can be packed per integratedcircuit doubles every 18 months. Although this leads to the speed up of processorsexponentially, it also causes to the increase of power dissipation. Thus there is aneed for new techniques to reduce power dissipation. Two techniques are presentedin this thesis: exploiting narrow values and use of high performance comparators.With the use of narrow values a 36% reduction in power dissipation is achieved,and is presented in detail. This technique relies on the idea that some values insidethe registers can be represented with fewer bits than the datapath width. With thehelp of narrow values most of the significant bits of registers are disconnected frompower supply and thus power dissipation of these bits are reduced. We use spec2000benchmark programs in order to identify optimum register width, and present powersaving with using this approach. Additionally with narrow values we propose afast parity generation in registers. Finally, we propose the modelling of circuitswith polynomials in order to reduce the wake up time of circuits which uses sleeptransistors.Key Words: Microprocessors, Low Power Consumptionv