Obtaining the memristor model and the utilization of real devices in analog subthreshold circuits

It was understood that the memristor could model synapses facilitating transmission between neurons, enabling the creation of artificial neural networks. The use of memristors could simplify the hardware implementation of neural artificial networks, which are otherwise challenging to construct in hardware. Additionally, due to its capacity to provide switching capabilities akin to transistors while occupying less space and consuming lower energy, memristors are envisaged for use in circuits where transistors are currently employed for switching purposes. This positioning has rendered memristors significant in the field of neuromorphic engineering. One of the bio-inspired circuits where memristors could be employed is the central pattern generator (CPG) circuit, introduced by Nakada et al. This circuit, akin to neurological patterns in animals' brains, generates signals for rhythmic movements like walking, running, and breathing. Transistors in this circuit operate in subthreshold regions and consume minimal energy. Köymen highlighted the advantages of incorporating memristors in this circuit. Measurements have been taken from memristors which in two different structures: Au/TiO2/TiO2-x/Au and Pt/TiO2/TiO2-x/Pt. These results have been analyzed. Accurate simulations are essential for the effective integration of the produced devices into circuits. Accurate simulations, in turn, necessitate a proper modeling of the fabricated devices. In this thesis, SPICE and Verilog-A models were derived for the generated devices, using curve fitting, phenomenological modeling, parametric analysis and utilizing equations from the quasi-static memdiode (QMM) model introduced by Saludes-Tapia et al. due to its similar behavior. Subsequently, the utilization of these models within circuits was investigated. The effects of serial and parallel connections, depending on the circuit's nature, were explored. They were applied to both CPG and the CPG's constituent HCO circuits, and their impacts were assessed. Following the memristor-embedded circuit simulations, layouts for the circuits were created. An optimization process was performed to fit these layouts into an even smaller area, revealing the potential for further reduction in size for these circuits.