Design of capacitance multiplier circuits for integration

In this thesis, five different capacitor multiplier circuits are proposed using the Current Feedback Operational Amplifier (CFOA) as the active circuit element. To reduce power consumption, dynamic threshold voltage MOSFET (DTMOS) transistors are employed in the internal architecture of the CFOA. The first design proposes a grounded lossless negative capacitor multiplier circuit using one CFOA, four resistors, and one grounded capacitor. The subsequent designs are lossy capacitor multiplier circuits that include one CFOA, three or four resistors, and one grounded capacitor. Mathematical analyses for each proposed circuit are conducted under both ideal and non-ideal conditions. Simulation results are obtained using the SPICE simulation program with 0.13 µm IBM CMOS technology parameters. The amplitude and phase responses of the input impedance of the lossless capacitor multiplier circuit are examined for various scenarios, including changes in process, temperature, supply voltage, and multiplication factor. To validate the lossless design, experimental studies are conducted using the commercially available AD844 integrated circuit.