Modelling and improving cache reliability

Since cache memories take the largest fraction of on-chip real estate today, they aremore vulnerable to soft errors, as compared to many other components of computing system.We first focus on a soft error model for L1 data caches. AVFC (Architectural VulnerabilityFactor for Caches) is the probability with which a fault in the cache be visible in the finaloutput of the program. We then propose three architectural schemes for improving reliabilityin the existence of soft errors. Our first scheme prevents an error from propagating to thelower levels in the memory hierarchy by not forwarding the unmodified data words of a dirtycache block to the L2 cache when the dirty block is to be replaced. The second schemeproposed selectively invalidates cache blocks to reduce their vulnerable periods, decreasingtheir chances of catching any soft errors. Based on the AVFC metric, our experimental resultsshow that these two schemes are very effective in alleviating soft errors in the L1 data cache.By using our first scheme, it is possible to improve the AVFC metric by 32% without anyperformance loss. The second scheme enhances the AVFC metric between 60% and 97%, atthe cost of a performance degradation which varies from 0% to 21.3%. To reduce theperformance overhead caused by cache block invalidation, we also propose a third schemewhich tries to bring a fresh copy of the invalidated block into the cache via prefetching.