Yüksek hızlı analog/sayısal dönüştürücüler uygulaması için 1.5ns ile 8ns gecikme kilitlemeli çevrim tasarımı ve serimi

As the VLSI technologies decreases to sub-micron and increases the clock frequencies the demand to correctly align the clock frequency with input data increases. On the other hand, as the clock period is reduced in high-speed applications the timing jitter becomes crucial border in clock distribution networks. Also by decreasing the clock period, if the jitter and skew remain constant, the total clock phase error increases. This issue will hugely affect synchronous system properties like setup and hold times in flip-flops, data access times and the precision of internal control signals. The process, temperature and voltage variation effects on clock are another problems that cause timing jitter and need to be compensated with employing a DLL to stabilize the delay of the unit delay across PVT. In this work, a 120MHz to 670MHz delay locked loop in 180nm TSMC CMOS process is presented to align the input clock and data of the 1.25GSPS high speed digital to analog converter. Three separate voltage controlled delay lines used to achieve a wide frequency range. An 8-Bit shift register is used to select the proper VCDL according to the reference input clock, this is happened by the last 4-Bit of a serial 8-Bit input code of shift register and will be discussed in detail. A TSPC based phase and frequency detector is used to achieve high-speed operation and acceptable rate of jitter to produce UP and DOWN pulses to control charge pump switches. A single ended charge pump is used to convert these UP and DOWN pulses to a control voltage through a loop filter to control the delay of the VCDL and lock the DLL to a one period delayed clock signal. In order to perform corner and monte-carlo simulations and evaluate the performance of the proposed delaye locked loop, a test bench with multiple input frequencies designed to apply different input clock frequencies to the DLL block. The full layout of this system is drawn to evaluate the effect of the parasitics and circuit mismatch. Then cycle to cycle jitter, peak to peak jitter, duty cycle error, settling time are simulated across PVT and monte-carlo results are provided.