Analog digital converters and design of a 6-bit adc using 1.5um cmos Vlsi technology
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Abstract (EN)
Analog-to-Digital converters are ubiquitous, critical components of software, radio and other signal processing systems. At sampling rates ranging from ~2MS/s to ~4 giga samples Per second(GS/s), resolution falls off by ~1 bit for every doubling of sampling rate. This behaviour may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADC's operating at multi—GS/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The ADC's range from flash, a parallel technique, which is the fastest, through integrating which is probably the most accurate but which also is the slowest. The flash architecture uses 2^N-1 comparators, where N is stated resolution. Flash converters often include one or two additional comparators to measure overflow conditions. All comparators sample the analog input voltage simultaneously. This ADC is thus inherently fast. The parallelism of the flash architecture has drawbacks for high resolution applications. The number of comparators grows exponentially with N. In addition the seperation of adjacent reference voltages grows smaller exponentially. Consequently this architecture requires very large IC's. It has high power dissipation, it is difficult to match components in the parallel comparator channels. Finally, increasingly large input capacitance reduces analog input bandwidth. In order to overcome these problems, variations on the flash architecture have been developed which use relatively few comparators yet retain good speed. Examples capable of GS/5 rates are the folded-flash and pipelined architectures. This study provides insight into all the three types of analog to digital converters mentioned above. Moreover, a 6-bit parallel analog to digital converter is designed using Tubitak Yital 1.5um double poly double metal process parameters.
Author
Sadiye Nergis Tural
Institution
How to Cite
Sadiye Nergis Tural (Master Thesis). Analog digital converters and design of a 6-bit adc using 1.5um cmos Vlsi technology, 2002, Yıldız Technical University.
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