Design of a multilayer cellular neural network emulator and its implementation on an FPGA device

Electronics engineering, which was once a subbranch of electrical engineering, became a main branch and separated into many subbranches in the near past. Image processing is one of these subbranches which is also an interdisciplinary engineering topic. Types of image processing are also increased and developed due to the technological advances. Nowadays there are many analog and digital systems, which are capable of realizing various image processing applications. One of these systems is called a cellular neural netwok (CNN), which was put forward as a structure of cells where the output of each cell is computed by using the inputs and outputs of the neighbouring cells. The CNN structure is used in not only image processing tasks but also other types of applications, such as chaotic systems and solving partial differential equations which are beyond the scope of this thesis. The CNN was firstly defined as a continous-time and discrete-space cell-grid. A CNN structure can be used in image processing by corresponding each input and output of an image processing system to the input and output of each cell. The 2-D grid of a CNN can either be implemented as an analog application specific integrated circuit (ASIC), or emulated on a digital hardware. The maximum resolution of the analog and digital implementations to date are 176x144 and 640x480, respectively. There are higher resolutions reported for the digital emulations, however, the frame rate of the emulation drops drastically. A recently introduced CNN emulator called a second generation Real-Time Cellular Neural Network Processor (RTCNNP-v2) is reported to be capable of processing full-HD 1080p@60 (1920x1080 resolution, 60 Hz frame rate) images in real-time. A single-layer CNN structure is generally used in the early CNN applications which is capable of realizing many image processing applications. However, it is either difficult or impossible to realize some applications with a single-layer CNN structure, e.g., algorithms that require more sensitivity, precision, carrying out computations with complex numbers, modelling systems with multi-order partial differential equations, etc. It is reported that these requirements can be met by the introduction of two- and multi-layer CNN structures. In this thesis, the design and implementation stages of the architecture of a generalized two-layer DT CNN emulator and a specialized multi-layer DT CNN emulator are proposed based on the RTCNNP-v2 structure, which are capable of processing full-HD 1080p@60 images in real-time. While a two-layer DT CNN emulator design is capable of realizing all the templates in the general mathematical model, a new measure of layer neigbourhood is defined for the multi-layer DT CNN emulation. This measure limits the intra-layer connections to only neighbouring layers. Furthermore, the proposed measure is extended to support far-neigbourhood interconnections. A two-layer RTCNNP architecture is implemented on an Altera Stratix IV GX 230 FPGA device, with a maximum number of 24 Euler iterations. The visible pixel rate and the pixel clock frequency of the prototype is 124.4 MP/s and 148.5 MHz, respectively, while the throughput is 124.4 MP/s.