An eg-ldpc based 2-dimensional error correction code for mitigating multibit upsets of sram memories

As SRAM memory chips manufactured with small feature size, low noise margins and low voltage level, MBUs (Multi Bit Upset) become the dominant contributor of the overall soft error rate. Therefore, Single Event Correcting–Double Event Detecting (SEC-DED) codes, such as Hamming codes, would be unable to mitigate the soft errors alone. Other conventional memory protection methods such as bit-interleaving in combination with SEC-DED codes and Triple Modular Redundancy (TMR) are not feasible either, as scaling up these techniques to cover large-scale MBUs will incur excessive increase in area, latency and power consumption of SRAM memories. One promising solution to mitigate MBUs with large widths is to construct two dimensional (2-D) ECC structures, which can provide scalable multi-bit error protection against large clusters of soft errors. Compared to conventional schemes with similar error coverage, 2-D ECC architectures offer significantly smaller latency, resource usage and power consumption figures. Recently, Euclidean Geometry Low Density Parity Check (EG-LDPC) codes are proposed to overcome effects of MBUs in memories. EG-LDPC codes have better multiple error correcting capabilities than conventional codes and they have low complexity and low delay decoders. Therefore, they are very suitable for fault tolerant memory applications. In this thesis, a 2-D error correction code architecture based on EG-LDPC and single parity check (SPC) code is proposed as a solution to MBU problem of SRAM memories. The proposed architecture uses (15, 7, 5) EG-LDPC as row encoding and SPC code for column encoding. In order to minimize decoding complexity and taking advantage of detection capability of 2D structure, a standard array decoder is utilized. The investigated architecture is compared with previously proposed Matrix code method. The proposed architecture is able provide over 95% error correction coverage up to 4 errors and a significant 100% error detection up to 12 bit errors. In terms of MTTFs, the proposed approach achieves 63% improvement over Matrix codes at fault rates of 10-4 and 10-5. Matrix codes and the proposed architecture are implemented using Xilinx XC6SLX16 FPGA (Field Programmable Gate Array) and comparison results in term of implementation complexity are provided.