Embedded design and implemetation of pedestrian detection system

mage processing based systems rapidly expand the application areas with developing image processing studies and technology. Object recognition applications such as face, licience plate, pedestrian recognition with computer vision systems is frequently encountered nowadays. In recent years, pedestrian recognition systems find its field of application on automotive technologies areas to prevent traffic accidents. Reports prepared on reasons of this accidents be motivation source for studies which is done in this area. According to the reports prepared by World Health Organisation (WHO), traffic accidents caused deaths of 1.200.000 person per year in the world and the vast majority of these deaths are pedestrians. In this study, a pedestrian recognition application was developed by using Histogram of Oriented Gradients (HOG) algorithm and Support Vector Machine (SVM). HOG algorithm which is frequently used as a feature extraction method in pedestrian recognition applications was implemented in FPGA hardware then classification of extracted features and pedestrian recognition are done by SVM software by microprocessor. In this thesis, a mechanism established including FPGA and microprocessor to implement designed system also a basic interface card designed for communicate with FPGA and microprocessor. Mobility and the power consumption are the first priority of selection that FPGA and microprocessor units mounted on assembled mechanism. Altera DE0 Nano application development board produced by Terasic company is used as a FPGA unit and BeagleBone application development board which use ARM architecture is selected as a microprocessor unit. The implemented system is trained with the 2000 train samples of NICTA pedestrian database and obtained 98.15% classification performance with 2000 test samples.