Fault tolerant microprocessor design

In this thesis, a fault tolerant microprocessor has been designed in order to operating correctly against faults. Microprocessors are used in safety-critical embedded system applications and they are main part of the system and their correct functionality is essential. With transistor scaling, circuits are more susceptible to errors and it leads to reliability concern in the systems. Besides the manufacture faults, wear-out factors, single event effects (SEEs), that occur because of the environmental factors such as radiation effects, cause from logical errors in combinational circuits, to upsets changing data, to destructive hard errors with increasing soft error rate. SEEs causes single event upsets (SEUs) which is bit-flips or changing the state on flip-flops, memory cells due to the impact of particles, such as neutrons and alpha particles. Although SEU is the major concern for some critical applications, multiple bit upsets (MBU) are also becoming important problems in designing memories due to the fact that the probability of MBU generation is increasing in modern technologies. Due to the these reasons, fault tolerant design is so necessary and crucial. Fault tolerance is the ability of a system to continue performing its intended function in spite of faults. In a broad sense, fault tolerance is associated with reliability. Redundancy is redundancy is the provision of functional capabilities that would be unnecessary in a fault-free environment. This can be a replicated hardware component, an additional check bit attached to a string of digital data, or a few lines of program code verifying the correctness of the program results. Hardware redundancy is achieved by providing two or more physical instances of a hardware component. Many hardware fault-tolerance techniques have been developed and used in practice in critical applications ranging from telephone exchanges to space missions. Especially in the embedded systems domain, it brings a number of penalties: increase in weight, size, power consumption, as well as time to design, fabricate, and test. The basic form of redundancy is duplication with comparison (DWC). Two identical modules perform the same computation in parallel. The results of the computation are compared using a comparator. If the results disagree, an error signal is generated. A duplication with comparison scheme can detect only one module fault. After the fault is detected, no actions are taken by the system to return back to the operational state. The most common form of passive hardware redundancy is triple modular redundancy (TMR). There are 3 identical modules in TMR and output is decided based on the majority voting. If one of the modules fails, the majority voter will mask the fault by recognizing as correct the result of the remaining two fault-free modules. A TMR system can mask only one module fault. A failure in either of the remaining modules would cause the voter to produce an erroneous result. Information redundancy is redundancy into the data. Because, errors in data may occur when the data are being transferred from one unit to another, from one system to another, or even while the data are stored in a memory unit. The most common form of information redundancy is error detection and correction (EDAC), which adds check bits to the data, allowing us to verify the correctness of the data before using it and, in some cases, even allowing the correction of the erroneous data bits with lower overhead. The simplest type of EDAC is a Single Parity Check which computes the exclusive-or (XOR) of the k data bits, and appends this single parity bit to the data block to form the overall coded block. This can only detect errors. Single Error Correction (SEC) codes which can correct a single bit error in a block are commonly used to protect memories and circuits when error detection is not sufficient. There are different types of SEC codes, a famous example being the class of Hamming codes. A Single Error Correction Double Error Detection (SEC-DED) code can be constructed from a Hamming code by adding a parity bit; this parity bit is used to identify single errors and avoid miscorrection (this is often referred to as an extended Hamming code. Matrix codes, combines Hamming and Parity codes to assure the improvement of reliability and yield of the memory chips in the presence of high defects and MBUs. Fault injection is a key to evaluating fault-tolerant techniques. Those approaches can be divided into hardware based fault injection and software based fault injection. Furthermore, software based fault injection can be classified as software-implemented fault injections and simulation based fault injections. One type of the simulation based fault injections, Verilog HDL,with the high observability and controllability can be obtained. Selection of open source microprocessor ,design of fault injection circuit, modification of the microprocessor writing an application code and analyzing the results are the steps of the fault injection to the microprocessor. First of all in order to observe the behaviour of a circuit when faults exist, a fault injection circuit has been designed. Natalius microprocessor, which is 8-bit Reduced Instruction Set Computer (RISC) processor, has been chosen as design under test. Necessary interfaces have been formed and all the units have been connected to each other. Then, results have been obtained. Register file is accessed frequently by the microprocessor. Arithmetic and logic operations are performed on register values. Therefore a fault, which occurs inside it, can effect whole system. That's why, fault tolerant techniques to protect register files have been examined in the literature. A new method, called as codeset, has been proposed by making use of the majority voter circuit of TMR, which is one of hardware redundancy method, and calculations of protection bits of matrix code. The key idea of the design is developing a method in order to protect register file against burst errors. So, codesets have been created. Moreover, random faults in a register can be corrected. A voting mechanism has been developed and wrong correction of the original data has been prevented because of the faults that occurs parity or check bits. This technique is cost effective and configurable because codesets can be created to protect data against up to 2, 4 or 8-bit adjacent or random errors in any register. In order to use the method in microprocessor, both 32-bit single cycle and pipeline microprocessors have been designed with MIPS architecture. One of the most safety critical usage of microprocessors is cryptography. Cryptographic algorithms can be implemented in MIPS easily. AES (Advanced Encryption Standard) is a very widespread symmetric-cryptography algorithm for encrypting data. FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) provide suitable platforms for implementations of the algorithm. Therefore, Advanced Encryption Standard (AES) algorithm has been chosen and crypto module has been integrated into MIPS microprocessor so as to create an application platform. Register files have been designed with fault tolerant techniques. By using fault injection circuit, simulations have been performed in different situations. Reliability is is the probability of a device performing its purpose adequately for the period of time intended under the operating conditions encountered. It increases with the fault tolerant design approach. In this study, reliability values have been calculated for the fault tolerant techniques. Designs have been synthesized by using Cadence RTL Compiler on TSMC 90nm process. Area, maximum frequency results have been given. Furthermore, reliability analysis have been made and results have been compared.