Leon3 microprocessor based system design

In this work, image encryption system was designed on a Field Programmable Gate Array (FPGA) by using JPEG (Joint Photographic Experts Group) image compression standard. Transmission of images comes into prominence after the development of internet technology. Also, the storage problem becomes evident while internet technology is developing. Minimization of the number of information carrying units is important for image data compression. Also, since the main target is reducing the memory and decreasing the bandwidth in communication, image compression techniques are very useful. In this area, JPEG is international standard due to the fact that it has high compression ratio and it does not cause of deformation of images. Nowadays, digital images and the security of videos come into prominence in areas such as television broadcast, video conferences, medical imaging. Security of data transmission is crucial as well. It is necessary to provide security of data or image by sending them in a channel. In this work, Tiny Encryption Algorithm (TEA) was used for encryption. TEA is suitable for embedded systems owing to high performance, ease of implementation, high speed, low energy consumption, low cost, and being lightweight. The TEA design's main aim is to provide minimum memory space and have maximum speed. Moreover, it uses Feistel Encryption type. As a result of this, when plain text is changed 1 bit, this reflects to output, which name is chipper text, as 32 bit. 128 bit key is used for encryption. Modified TEA was used in this work by changing the number of input bits. In standard TEA, input is 64 bit and it is divided left and right side as 32 bit. It was modified as the input of circuit as 72 bit so our left and right sides are 36 bit. However, key length is still 128 bit. The design of encryption and compression were implemented together in order to increase security level. The method is not like encryption of one image which is in JPEG format. Encryption and compression blocks were implemented as one hardware. Hence, if someone gets encrypted and compressed image, he/she can not obtain original image after decryption. Because the encryption was performed at the pixel level. To accomplish the JPEG image encryption system, JPEG encoder was designed in the beginning. JPEG encoder design includes Discrete Cosine Transform (DCT), Quantization, Zig-Zag reordering, Diffence Coding for DC coefficients, Run Length Coding for AC coefficients, and Huffman Coding blocks. The main aim of the DCT is to transform the value of pixels from spatial domain to frequency domain. The level of detail in an image is related to the frequencies. High spatial frequencies correspond to high levels of detail, while lower frequencies corresponds to lower levels of detail. The result matrix of DCT consists of 64 DCT coefficients. The next step in the compression process is quantization of the DCT matrix. It is the process of reducing number of bits needed to store an integer value by reducing the precision of the integer. The quantization process has the key role in the JPEG compression. The quantization cycle has readily apparent effects on an image. The low frequency elements which are close to DC coefficient have been modified. The high frequency elements have been reduced to zero. The human eye is much more sensitive to lower spatial frequencies than to higher frequencies so quantization is necessary for JPEG. This is achieved by dividing values at high amplitude frequencies in the matrix with larger values than the values by which are divided the amplitudes of lower frequencies. Due to rounding in quantization, it is the lossy step of JPEG standard. As a result, insignificant data in matrix is discarded. After doing the DCT transform and quantization over a block of 8x8 values, a new 8x8 block is obtained. This 8x8 block is traversed in zig-zag ordering. The reason for this zig-zag traversing is that we traverse the 8x8 DCT coefficients in the order of increasing the spatial frequencies. After the zig-zag reordering, first six elements of zig-zag vectors were encrypted by using TEA. These six elements have the lowest frequencies of each matrices. Therefore, they have the most effect on the image. First one of these six elements is the DC coefficient of 8x8 blocks. Other five coefficients are AC coefficients of 8x8 blocks. After the encryption, all pixel values are gathered again and Huffman Coding is started. In the Huffman Coding, there are Zero Run Length Encoding for AC coefficients, Difference Coding for the DC Coefficients and Encoding blocks. In the result of Huffman Coding Block, encrypted image bit stream is obtained. Some special blocks were used in order to design JPEG encoder. For DCT design, it is necessary that all input pixels have to be ready at the same time. In order to provide these inputs, ping-pong buffer was used. In ping-pong buffer, there are 8 registers and when the input is available, it is stored at the first register. Previous value of register is shifted to the next register. Hence, the buffer is sampled for each 8 clock cycle. After the 8 inputs are ready in registers, enable is activated in order to send these inputs to outputs. This block is necessary since inputs of DCT block are serial but 8 pixel values have to be ready at the same time in order to calculate DCT values. During these processes, input registers takes new input pixels. Therefore, there is no need to wait for DCT calculations or new inputs. Whole results were stored by using dual RAM structure. 1-D DCT and 2-D DCT results were stored at this RAMs and they were used alternately. This structure helps the designer about providing continuity of calculations. After the designing of image encryption and compression blocks on a FPGA, this hardware was added to the Leon3 microprocessor as a peripheral. Leon3 is a 32 bit SPARC processor which is implemented as synthesizable and open source VHDL model. It was primarily developed for space application by European Space Agency (ESA) and it is widely used in embedded systems and applications today. It is also the part of Gaisler Library (GRLIB) which includes IP cores for FPGA and ASIC designs. Full source code is available under the GNU GPL license. The GRLIB is designed in order to connect all IP cores to the bus which is Advanced Microcontroller Bus Architecture (AMBA) Advanced High Speed Bus (AHB)/Advanced Peripheral Bus (APB). In this work, hardware design was added to the APB of Leon3 microprocessor. Interface was designed in order to connect our IP to Leon3 core. Also, it is necessary to have a C program in order to manage flag operation of the hardware. C program was compiled by using cross compiler of Leon3. 288x288 pixels images were used in order to test the system. First, only DC coefficients of 8x8 blocks were encrypted and result images were given. Then, DC coefficients and first five AC coefficients of 8x8 blocks were encrypted and result images were given. These two methods were compared by calculation their Peak Signal to Noise Ratio (PSNR). UART of the Leon3 microprocesssor was used for transferring of image matrices.