Lojik kilitleme ve çoklu-darbeli test üretimi için hata emülasyonu teknikleri

The testing phase for testing the actual, post-manufactured chips is what is referred as test or testing in digital system design industry. Recently, multi-cycle tests that offer high test quality have been proposed. Multi-cycle tests are accomplished by feeding the input vector constantly and putting the circuit in functional mode for multiple cycles. Multi-cycle tests are often needed by partial-scan circuits and circuits with multiple clock-domains. In addition, the VLSI Test community is interested in multi-cycle tests because they can reduce the test time and cost by detecting more faults with the same test vector. However, the fault simulation of multi-cycle tests is computationally expensive. In literature, no fault emulation method for multi-cycle tests has been proposed yet. In this thesis, a new multi-cycle test generation algorithm is proposed and its fault emulation method is developed. With the help of our fault emulation method, we accelerate the process of multi-cycle test generation. In our multi-cycle test generation method, dynamic single fault activation technique has been used. Later, this method is modified to enable multiple fault activation, which is then applied to another computationally expensive problem. The process of determination of key gate locations in the logic locking problem in hardware security is accelerated by the second emulation method proposed in this thesis. The effectiveness of both emulation methods is evaluated on the ISCAS'89 benchmark circuits and results are presented.