New opportunities in MOS-only filter design

Research on analog design automation emerges on troublesome manual design cycles in analog circuit design. Manual circuit-sizing in analog design is a time consuming process since non-idealities in a practical circuit result in serious deviations from theoretical calculations. Moreover, selection of the optimal solution among different performance parameters becomes very critical and challenging process, especially when circuits become complex. In this regard, reformulation of conventional equations and integration of the designer's knowledge as well as experience with simulation-based data encourage novel computer-aided automation algorithms. Moreover, MOS-Only circuit design has been gaining big importance because it does not necessitate large chip area. The most important requirement of the MOS-Only design is to understand physical properties and operating mechanisms of the basic components in electronics. Furthermore, in Very Large Scale Integrated (VLSI) circuit design, large numbers of circuits have been sized by hand-calculations and iteratively chain of computations. In this respect, there is a wide gap for design automation proposals, which incorporate knowledge and experience of designer and re-formulation of the conventional equations in this area. As a result, different algorithms or methods are arisen from this urgent demand and rapid growing of VLSI technology. One of the most popular ways, to design an analog filter is to make use of the intrinsic parameters, gate-to-source capacitance ( ) and transconductance ( ), of a MOSFET. This kind of circuits has very small chip area without employing external passive elements. Also, these circuits make use of only MOS transistors without any external active elements or analog building blocks. In comparison of MOS-Only structures with the other topologies, there are several current mode filters in the literature that employ active circuits like Fully Differential Current Conveyor (FDCCII), Current-Controlled Current Conveyors (CCCII), Current Differencing Transconductance Amplifier (CDTA) , Multi Output Second Generation Current Conveyor (MO-CCII), Dual output CCII (DO-CCII), Voltage Differencing Transconductance Amplifier (VDTA), Modified Current Follower Transconductance Amplifier (MCFTA), Operational Transconductance Amplifier (OTA), Dual Output Current Controlled Current Differencing Transconductance Amplifier (DO-CCCDTA), Differential Voltage Current Conveyor (DVCC) etc. They suffer from high layout area and low operating frequency; because they include high numbers of transistors and passive circuit elements. In this thesis, two novel different methods are presented for the automation of design of MOS-Only filters and MOS-C structures. Proposed methods can be easily implemented for different technological processes. Furthermore, presented novel architectures by using these methods can be easily employed in different application areas. It should be noted that in order to automate the design cycle for the presented MOS-Only structures, it is essential to model fundamental small signal parameters by using surface fitting and advanced polynomial regressive methods. However, it is unavoidable that better modeling accuracy comes up with design complexity. To avoid design complexity, it is important to choose the proper method for the proposed circuits by taking into consideration pre-design specifications. First method is MOS-Only design automation based on polynomial regression. In this method, some high order polynomial functions are fitted to the small signal parameters of transistors. These functions connect the pre-defined design constraints to design variables such as dimensions, bias voltages/currents. Defined formulations based on different simulators' data are the result of surface fitting by using computer assisted methods and they can be easily arranged for different technologies. In the end of automation cycle based on the first method, all aspect ratios, bias currents and voltages are obtained in the MOS-Only circuit. Also, this method brings high computational accuracy for the calculation of post-design specifications. Second method is defined as convex approximation. Convex programming is used for a wide range of applications from mathematics up to deep engineering problems. For electronics, it attracts designers for the sake of computational speed and globally optimal solution. In comparison to the first method, it is aimed to obtain all design parameters by using posynomial and monomial formulations. On the other hand, small signal parameters' modeling may not be possible in every technology with the high accuracy using monomials or posynomials, which are specific sets of the fitting functions. In this work, design parameters are modeled with TSMC CMOS 0.18µm process and results are compared with the aforementioned method comprehensively. Finally, subthreshold operation is modeled using polynomial regression for MOS-Only and MOS-C circuits. In this region, it is possible to develop different circuits for a wide range of low frequency applications. All dominant small signal parameters are reformulated for this region using piecewise polynomial regression with high accuracy. All proposed methods in this thesis are developed for TSMC CMOS 0.18µm process. It should be noted that all coefficients in the models should be reobtained for different technologies. Besides, all circuit schematic and post-layout simulations are realized in CADENCE environment by using TSMC CMOS 0.18µm technology. In conclusion, it is aimed that the designed circuits with proposed methods give new opportunities to the electronics engineers.