High fan-in differential capacitive-threshold-logic implementation with an offset-compensated comparator

A high fan-in threshold logic gate with a relatively low propagation delay is proposed. The gate utilizes a comparator capable of compensating the input referred offset without the need to implement a feedback loop by implementing a capacitive cross-coupling of the two inverters in the comparator. The gate performs sum-of-product and thresholding operations by individually setting the minimum sized MOSFET capacitors. This is achieved by setting the threshold and input voltages with digital logic levels. The operation of the gate is dynamic and comprises two phases, in which the inputs and threshold setting are done during the reset phase while the comparator provides the resultant at the evaluation phase. A second topology is proposed to reduce the propagation delay by implementing two more switches driven by a second clock. The thesis presents the analysis, properties, and limitations of implementing a high fan-in threshold logic gate by analyzing six gates of fan-in 15, 31, 63, 127, 255, and 511. Post-layout analysis and results of the 511 fan-in are provided. The design is then verified with CMOS 65 nm technology under all process corners with a distribution of process and mismatch of 3σ.