RISC processor design on FPGA and BMS application

Fast calculations within Battery Management Systems (BMS) with low power use is important for the safety of humans and the environment. To accomplish this goal, BMS requires a fast processor which does the calculations. RV32I base integer instruction set, which is part of RISC-V instruction set architecture (ISA), is one of the candidates with its robust RISC architecture. The issue of storing electric energy for future use became crucial with the increasing demand for portable electronic devices, electric vehicles and temporary power storage. Li-ion batteries are one of the most reliable choices in today's technology due to their energy density, efficiency, and cycle life. However, they should be monitored and managed for safety and reliability reasons. BMS monitors and manages the batteries. There are many parameters to measure from Li-ion battery and to calculate from the measurement. For example, the voltage of the battery, charge-discharge current, temperature, state of charge (SOC), state of health (SOH), etc. Some of the calculations even include the time domain, and these parameters are so essential to be known they indicate the remaining time to charge fully or the remaining time to discharge fully, the charges left in the battery, the condition of the battery, and many more. This study aims to design, implement and test the designed RISC processor. In this thesis, a 7-stage pipelined RV32I core has been described in Verilog HDL and implemented on a Basys-3 FPGA board with 100MHz clock frequency using the Vivado Design Suit. When the core is separated, it can reach 150 MHz frequency on the Basys-3 board and 270 MHz frequency on the Kintex-7 board. The core executes instructions as described in ISA. To communicate with other devices, such as a personal computer, a UART module is also described in Verilog HDL and PuTTy software is used as a serial communication terminal application for the personal computer. For analog data, LogiCORE XADC IP is used, and a compatible module is also described in Verilog HDL to read external voltage levels from the sensors. This study contributes a 7-staged pipelined RV32I core to literature, and it can be improved in the future to more generalized or more specific versions.