SAR ADC'nin davranışsal modellenmesi

During the last two decades, the usage of integrated circuits have been increased in modern electronic systems due to development of the process technology while offering low cost and high performance. Also it leads to powerful digital signal processing techniques that require an analog-to-digital converter (ADC) to communicate with analog world. Nowadays, ADCs (Analog to Digital Converters) become very popular with the increase of mixed signal applications in electronic. Moreover, energy consumption have been the most significant topic in the last decade. Amongst various ADC architectures, SAR (Successive Approximation Register) ADC becomes most common ADC architecture as it is suitable for low power, medium to high resolution and medium speed applications. Previously, Capacitive DAC array was the most critical block of SAR ADC, due to the matching of the elements in the DAC that determines the total noise contribution and linearity of SAR ADC. Developing technology gives an opportunity to implement the DAC with smaller area and better matching and as a result it is possible to reach higher resolution with SAR ADC. However other non-idealities of the blocks in SAR ADC must be taking into account to attain higher resolution together with high speed. The increase of transistor number in the circuit due to the development of process technology cause long transistor-level simulation time that can be take days to complete. However, Matlab or Simulink models offer fast and accurate results that can be used to determine design specifications or to investigate exist architecture. In this thesis, complete behavioral model of a two-step SAR ADC architecture is studied in Matlab Simulink environment to analyze non-idealities of capacitive DAC, comparator, opamp, clock signal and reference voltages by using charge equations that are derived to find transfer functions of the SAR-ADC. Since all block parameters are set as a variable, it is possible to use model for any Nbit SAR ADC architecture with small changes. Moreover the model shows promising results with respect to measurement results of the SAR-ADC that is also studied in the thesis. As a consequence, accomplished model is a powerful tool that helps to understand basic and complex behaviour of the SAR ADC and provides information about limiting factors for ADC in a short time period compared to transistor-level simulations.