A scalable cache coherent memory architecture for reconfigurable computing

Field programmable gate arrays have significant potential for high performance computing since it provides reprogramming and application-specific efficient hardware design. However, application-specific hardware architectures are required to be defined by low level programming languages that have hard design processes. Recent researches allow efficient hardware design with high-level programming languages. High-level synthesis (HLS) compilers provide ease of programming by automatically converting software programs to register-transfer level design. These compilers require an efficient, coherent and special memory architecture on reaching data, while generating efficient and independent data paths, and finite state machines. In this thesis, a scalable cache coherent memory architecture that feeds the generated data paths constantly, shortens the latency time and ensures that the data is coherent, is proposed and implemented in Verilog language for an HLS compiler. This memory architecture following directory-based write-update protocol has a novel cache coherence protocol. Number of coherent caches and directories, specified by the compiler, are arbitrary. Coherent caches can belong to different coherence domains and the directory manages coherence traffic only between caches that are in same coherence domain. It is verified by software-hardware comparison that the protocol integrated to the compiler runs without error in hardware generated for 51 benchmarks. In these tests, there are 2 directories connected to L2 caches, while number of coherent L1 caches that varies depending on the implemented algorithm is in the range of 2 and 39. The scalability and performance potential of the model are demonstrated.