Sequential large multiplier designs for FPGAs

Large operands are used in cryptography, signal processing and multimedia applications. To achieve high-speed, the multiplication of the large operands is performed by a large multiplier hardware. These circuits can be designed by using embedded arithmetic blocks offered by the state of the art FPGAs. This thesis presents ten sequential large multiplier designs that can be mapped on FPGA platforms. First three of the designs use symmetric embedded multipliers and following three designs use asymmetric embedded multipliers. These six designs differ depending on the number of embedded multipliers usage. The following two designs can either multiply large numbers or perform simultaneous multiple smaller multiplications. The final two designs use Karatsuba-Ofman multiplication method to increase performance with symmetric embedded multipliers. The first design is single precision while the second one is multiple-precision like the previous two designs. 64-bit to 2048-bit multiplier implementations of Sequential Large Multipliers are modeled and synthesized. Compared to a fully combinational 256-bit multiplier synthesized using vendor's tool, the 256-bit implementation of sequential large multipliers with multiple asymmetric multipliers uses 15 times less resources and has 1.94 times more delay. Speed disadvantage of sequential multipliers is solved by multiple precision designs. For example the delay per multiplication of 2048-bit multiple precision implementation at 256-bit mode is four times less compared to combinational design synthesized with vendor's tool. Also the multiple precision design uses 50% of the DSP slices and the combinational design uses 90% of the DSP slices on the target FPGA platform.