Sıralı elemeli ve listeli kutupsal kodçözücü'nün FPGA uygulaması

Polar Codes are the first asymptotically provably capacity achieving error correc- tion codes under low complexity successive cancellation (SC) decoding for binary discrete memoryless symmetric channels. Although SC is a low complexity algo- rithm, it does not provide as good performance as a maximum-likelihood (ML) decoder, unless sufficiently large code block is used. SC is a soft decision decod- ing algorithm such that it employs depth-first searching method with a divide and conquer approach to find a sufficiently perfect estimate of decision vector. Using SC with a list (SCL) improves the performance of SC decoder such that it provides near ML performance. SCL decoder employs beam search method as a greedy algorithm to achieve ML performance without considering all possible codewords. The ML performance of polar codes is not good enough due to the minimum hamming distance of possible codewords. For the purpose of increas- ing the minimum distance, cyclic redundancy check aided (CRC-SCL) decoding algorithm can be used. This algorithm makes polar codes competitive with state of the art codes by exchanging complexity with performance. In this thesis, we present an FPGA implementation of an adaptive list decoder; consisting of SC, SCL and CRC decoders to meet with the tradeoff between performance and complexity.