Taşınabilir ölçü aletleri için 8-bit 2 GSPS ayrık zamanlı ardışık yaklaşımlı analog sayısal çevirici tasarımı

A successive approximation register analog to digital convertor (SAR ADC) is a type of ADC that converts a continuous analog signal into a discrete digital representation for all the quantization levels as possible. For this thesis the SAR ADC is consist of a gain stage, a split capacitor array digital to analog convertor (DAC) block, and a SAR block to supply the requirements for high bandwidth real-time oscilloscopes. As soon as the bandwidth requirements extend beyond the sample rate capability of the available ADC, it becomes necessary to find other techniques to utilize available ADCs to meet those extended requirements or design a new generation ADC. Time interleaving (TI) is a common technique to extend the performance of existing designs. The ADCs are used as parallel. Each ADC provides a sample rate at least half the total sample rate required to meet the Nyquist requirement. The time interleaved SAR ADC is separated in 10 sub-ADC blocks, each sub-ADC is consist of 10 SAR ADC and clocked 36° out of phase. Data is stored in the memory behind each ADC, and once the acquisition is completed, the complete 2GS/s representation of the signal could be reconstructed by demuxing the data. The time interleave technique has been used by all the major oscilloscope structures to get the performance up into the GHz range. The real-time oscilloscope needs a fast and high bandwidth ADC. Based on this purpose, an 8-bit 2GS/s time interleaved SAR ADC is designed as usable in high bandwidth portable measurement devices especially real-time oscilloscopes. In this thesis, a reliable and feasible 8-bit 2GS/s SAR ADC with 2GHz bandwidth is presented using 180nm CMOS technology. A comparator consists of a latch and 5 amplifier with 3 of them are offset cancelled. The simulation results of the comparator is available in the relevant section. A fully differential DAC is consist of a sample & hold circuit and it is generated as split capacitor array DAC. The simulation results of the DAC is available in the relevant section. The DAC is driven by the SAR logic. The SAR block consist of a phase shifter with 9 D flip flops, a register array with 9 D flip flops, and one more register array with 8 D flip flops. The simulation results of the SAR logic is available in the relevant section. The SAR ADC processes with the overdrive-recovered amplifiers, offset cancelled comparator, and charge injection rejected split capacitor array DAC. Also the sample and hold procedure is completed by DAC block. The designed TI-SAR ADC is simulated and all the differential non-linearity (DNL), integral non-linearity (INL), signal to noise ratio (SNR), spurious free dynamic range (SFDR), signal to noise and distortion (SINAD), effective number of bits (ENOB) characterizations are determined.