Investigation of electrical properties of MOS structures with telluroxide (TeO2) interface

In this thesis study, Al/TeO2/p-Si metal/oxide/semiconductor (MOS) structure was obtained by doping telluroxide (TeO2) material to the metal/semiconductor interface by thermal evaporation method. First of all, the crystal orientations of the TeO2/p-Si oxide layer were determined by the X-ray diffraction (XRD) method. Electrical characterization of the obtained Al/TeO2/p-Si (MOS) structure at room temperature and in the dark was carried out by current-voltage (I-V) and capacitance-voltage (C-V) measurements. From the I-V results, the ideality factor (n) value was calculated as 1.55 and the zero supply barrier height (B) value was calculated as 0.76 eV. The fact that the ideality factor value of our structure is greater than 1 is attributed to the deviation from ideality due to the presence of the oxide interface film between Al/p-Si and the interfacial state distributions, as well as the high series resistance of the neutral region of the p-Si semiconductor layer. Series resistance (Rs) analyzes were also carried out using the Norde and Cheung method. Additionally, frequency-dependent C-V and conductivity-voltage (G-V) changes of our Al/TeO2/p-Si (MOS) structure were examined. All results were interpreted by comparing them with the literature. In conclusion; telluroxide (TeO2) oxide material is a potential alternative material to silicon oxide material used in device technology.