Transistör düzeyi simülasyonlara dayanan zamanlama verimi tahmini için sayısal devrelerin hızlı ve doğru istatiksel zamanlama analizi

As the Integrated Circuit (IC) technology scales down to deep sub-micron regime in terms of sizes of transistors used inside circuits, the IC manufacturing process suffers from circuit parameter variations, which cause uncertainties in the speed of the chips. The statistical variations of manufacturing process have increased to a non-negligible level, which necessitates statistical timing analysis considering the variations. As a result of the parameter variations, each manufactured chip of the same circuit has different parameter values and thus a different speed performance. The manufactured chips, which pass the speed tests, are packaged for marketing and others that fail the tests are discarded. One of the main aims of statistical timing analysis is to estimate timing yield, which is simply the fraction of chips that pass the speed tests. Almost all proposed statistical timing analysis methods for digital circuits are block (gate) level methods and they are called statistical static timing analysis (SSTA) methods, as they are direct generalizations of deterministic static timing analysis (DSTA) to the statistical case. However, block level statistical timing analysis lacks accuracy as it contains many approximations. In this thesis, we try to fill the gap for accurate statistical timing analysis based on transistor level circuit simulations. For this purpose, we first propose a new comprehensive statistical timing analysis tool that combines different techniques in the literature for modeling variations and extracting the statistically critical paths in a circuit. But our main novel contribution is timing yield estimation using importance sampling in a novel manner in order to speed up transistor level Monte Carlo (TL-MC) statistical timing analysis for obtaining both an accurate and efficient timing yield estimation method. We test our method on ISCAS?85 circuits and the results show that our IS based yield estimation method improves the speed performance two orders of magnitude on the average.