Uçucu olmayan belleklerde büyütme koşullarının yük-tuzaklamaya etkisi

Until recently, memories have been a critical bottleneck for the computer industry. Many research based (revolutionary) devices are in the research arena, however, technical concerns such as integration with the current semiconductor manufacturing processes and the feasibility prevent them from being mainstream. In contrast, charge trapping based memories are the evolutionary improvement to the currently ubiquitous floating gate (FG) based nonvolatile memory. This is predominantly due to their superior scalability and reduced leakage compared to FG based memories. This work attempts to investigate the influence of the deposition condition on charge trapping based non-volatile memories for two different gate stacks. The first one involves ZnO as the charge trap layer. This single-step grown ALD has the advantage of having low contamination and manufacturing simplicity. The second type of device uses Ge2Sb2Te5 as a charge trap memory. The nature of the defect states is different in the two materials, and hence the variation of the trap density with temperature.