Voltage controlled oscillator based low supply voltage microbolometer readout circuit

This thesis presents a novel, almost digital approach for microbolometer readout circuits to overcome the area and power dissipation bottlenecks of analog-based classical microbolometer circuits. A voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is utilized instead of a capacitive transimpedance amplifier (CTIA) in classical readout circuits. This approach, which has not been reported before, produces both the required gain in the microbolometer input circuit and directly digitizes the microbolometer pixel signal. In this way, the need for large capacitances (on the order of 10- 15 pF for each column) at the CTIA circuit and voltage headroom limitation of classical microbolometer circuits are eliminated. Therefore, the proposed architecture permits to design of readout circuits with reduced pixel pitch and lower power supply, leading to higher resolution FPAs (Focal Plane Arrays) with lower power dissipation. This study also describes a method to compensate bias heating effects for microbolometer readout circuits using a finely adjustable CMOS resistance as a reference. The proposed self-calibrated cooler-less structure dynamically modifies CMOS resistance during the integration time. This compensation structure also includes a feedback loop, which forces the oscillators to work in the linear region. The proposed self-calibration circuit is designed and simulated using a 65-nm process node and gives promising results to keep the output in the desired window up to 10K of substrate temperature changes. A test circuit has been designed and fabricated at TSMC 65nm Multi-Project Wafer (MPW) run to validate the proposed architecture. The prototype readout IC includes a 4$\times$4 pixel array, a 1$\times$4 reference array, 2 VCO-based column readout, a timing generation logic, and a bias generator. The measurement results indicate that the proposed architecture can yield a gain of around 2.5 Counts/$\Omega$. The noise of the proposed architecture is measured as 2.6 Counts. These two parameters yield a 55mK noise equivalent temperature difference (NETD), slightly above the state-of-the-art microbolometer readout circuits. The gain graphs also show that the proposed architecture has an inherent high dynamic range (HDR) ability due to the gain non-linearity of the oscillator structure for large input voltages. In addition, the proposed architecture dissipates around 79$\mu W$ power per column readout, which is almost one-third of the classical microbolometer circuits. The column readout occupies around one-tenth of the layout area of the classical microbolometer readout circuits. These two features make this architecture suitable for higher resolution lower power microbolometer readout circuits.