Yüksek band genişlikli 8-bit 20 Msps SAR ADC

Real time oscilloscopes require very high speed analog to digital (A/D) conversion. 1 GHz bandwidth is common among mid-end oscilloscopes today, whereas up to 40 GHz bandwidth can be achieved by state of the art, high-end oscilloscopes. A/D converters in such oscilloscopes need to be 2 Gsps and 80 Gsps respectively. Due to high bandwidth of the input signal, and difficulty of maintaining a linear, low jitter and low noise analog front-end, most oscilloscopes use no more than 8-bits of resolution in their A/D conversion stages. Other than achieving raw speed, lowering the power consumption of the A/D conversion becomes important for a certain class of battery powered, hand held oscilloscopes. Successive approximation register (SAR) type A/D converters have recently gained popularity in high speed applications due to their inherently low power consumption. To compensate for the relatively low conversion rate of the SAR ADCs, time interleaving of multiple A/D converters can be used. To have a smaller number of A/D converters in a time interleaved application, it becomes necessary to design a high bandwidth, fast and small SAR A/D converter. The purpose of this thesis is to demonstrate the design of such an A/D converter, using a standard 180nm CMOS process, for future work on time interleaving. Main specifications of the A/D converter are 1 GHz analog input bandwidth, 20 Msps sampling rate, 8-bits of resolution, and more than 6 effective number of bits at Nyquist frequency across process, supply, temperature, and chip to chip variations. To help reduce mismatch effects during time interleaving, the A/D converter is offset cancelled, and voltage references will be shared. Capacitor mismatch effects will not be pronounced for 8-bits of resolution. 100-way interleaving of such an A/D converter will be needed to design an 2 Gsps oscilloscope A/D converter, which is out of the scope of this work. Optimization of the design for lowest possible power consumption and smallest area is also beyond the scope of this thesis. In this work, a reliable and feasible 8-bit, 20 Msps SAR A/D converter with 1 GHz bandwidth is presented using 180 nm standard CMOS process. A five stage comparator with 3-stage output offset cancellation is designed, characterized using simulation and laid out. A fully differential capacitive DAC driven by the SAR logic is designed and characterized using simulation. Three reference buffers for Vref+, Vref- and Vcm are also designed and characterized via simulation. Finally, the A/D converter using an effective timing pattern is constructed and characterized for offset, differential linearity (DNL), integral linearity (INL), spurious free dynamic range (SFDR), signal to noise and distortion (SINAD), signal to noise ratio (SNR) and effective number of bits (ENOB). Simulations indicate that at full Nyquist bandwidth, the A/D converter exceeds 6 ENOB across process, voltage, temperature and chip to chip variation, with a nominal results of 7.2 bits. At a low 1 MHz input frequency, the nominal corner shows an ENOB of 7.95. Power consumption is typically 15mW excluding reference buffers, which will be shared during interleaving.