Reducing static energy dissipation of data holding components of modern microprocessors

Mobile devices which are running on limited battery needs low power consumption and long stand-by duration more than ever. However modern microprocessors dissipate more static energy as CMOS process technology shrinks. In this thesis data holding components of the modern microprocessors are examined. SRAM tables are analyzed by means of performance, power consumption and area.Thesis offers a power gating technique for data holding components which consists of SRAMs by exploiting narrow values and architectural state of the superscalar microprocessor. Register file is selected to prove our idea. Register file rows are literally put to sleep depending of their architectural state and narrowness. Narrowness indicates that a value can be shown by fewer bits than the data path width of the microprocessor. While upper order bits of a SRAM row are put to sleep depending on narrowness, a whole row can be put to sleep depending of the architectural state of the microprocessor. However physical layout of the SRAM tables prevents the straightforward implementation of the sleep decisions.Static energy dissipation is reduced by %42 and as a byproduct of this technique; dynamic energy is reduced by %32. Silicon area and microprocessor performance is kept constant compared to the baseline microprocessor.