Complexity-effective rename table design for rapid speculation recovery

Register renaming is a commonly used technique to remove false data dependencies in contemporary superscalar processors. This is done by assigning physical registers to registers defined in architectural design during the decoding process of the instructions in the processor. These assignments are kept in an alias table.When superscalar processors use techniques such as branch prediction the processor may reach a state it should not be in as a result of a misprediction. Instructions fetched mistakenly need to restore the rename assignments and return to a correct state.In contemporary processors the techniques which restore the rename table either sacrifice restore speed or hardware complexity. This study shows an extendable technique which has less hardware complexity, yet can restore the rename table in at most two clock cycles.The design proposes the use of differently sized FIFO queues for each architectural register to hold checkpoints. This study shows that the proposed structure performs better than existing techniques except in a few exceptional cases.Besides the rename table design, a study was also done on determining the optimum FIFO queue size for each architectural register without losing performance. This study proposes the use of genetic algorithms to successfully balance area usage and performance in a reasonable amount of time.