Design and implementation of a new cellular neural network emulator on FPGA for real time video processing

The Cellular Neural Network (CNN) concept was first introduced by Prof. Leon O. Chua and L. Yang at the University of California at Berkeley in 1988 during the course of an ONR (Office of Naval Research) project (N0001489J1402) entitled "Nonlinear Circuits and Neural Networks" which ran from December 1988 through November 1997. Later, as a result of the work carried out in collaboration with Prof. Tamas Roska of the Hungarian Academy of Sciences, Budapest, Hungary, during 1992-1993, Profs. Chua and Roska developed the CNN Universal Machine architecture at Berkeley. This architecture was first implemented on smaller scale (64×64) and later on larger scale (128×128) analog chips. However the development of analog chips had been rather slow and has some drawbacks. The fact that the equivalent bit accuracy of these chips is only 7-8 bits although their operation speed is quite high, and that the chip with the highest number of processors fabricated so far has only 128×128 cells and lastly the fact that the works on the 256×256 chip have not so far been completed, have led the researchers to start working on the digital emulations of CNN.In this thesis a new FPGA architecture for the emulation of the CNN structure is designed, implemented and tested with an edge detection application. This architecture is fast enough for real-time processing of video signals and is capable of taking a VGA signal, processing it in real-time and displaying the output on a VGA monitor. Furthermore, in order to lower the system cost, the design has been carried in such a way that the system does not require an external memory (RAM). The new structure provides a fast general purpose solution for digital image processing applications.In this thesis a step-by-step approach is using to achieve the ultimate goal. In doing so, first a CNN emulating processor structure is developed without paying any attention to speed. Then this structure is modified in order to make it function in a pipelined manner to increase speed and the processors have been laid out in the form of a 1-D array which enables the simultaneous functioning of the processing units.As the design environment, Xilinx ISE software and the schematic editor of the software have been used. At first, the design has been transferred to the PC environment by the use of the schematic editor of ISE software, and then the design errors have been found by simulation and corrected. Having seen the simulation in working order, the design has been implemented on the FPGA board and tested. In the test process, a logic analyzer core on the FPGA, which has been generated by the Xilinx ChipScope Pro software, has been used to find out the erroneous part of the design by observing the signals of the working circuit on FPGA, on the PC monitor and the design is then corrected accordingly.As a result, a new CNN emulator architecture for real time progressive video processing with 3×3 CNN templates is proposed and implemented on a Xilinx Virtex-II 3000 FPGA in Celoxica RC203 board, which does not require external memory. Implemented system is tested with 640×480 pixels 60 fps monochrome VGA input and the output video is observed on a VGA monitor.The emulator architecture implemented on FPGA has been awarded the First Prize in the Academic Innovative Embedded System Design category of CPU Turkey 2008 contest.