SONATA: Specialized address registers to reduce power consumption

Current computing systems use page tables to perform address translation. Modern computers make 5 memory accesses to obtain a translation. This adds a serious amount of overhead to the memory access. The granularity of the address translation is typically defined by the page size employed in the system. In current systems, there is a significant discrepancy between the page size (typically 4 KiB) and the word size (8 bytes in a 64-bit system CPU). As a result, the register file in the processor fills up with partially redundant memory address operands that point to different words in the same virtual page. Furthermore, the Translation Lookaside Buffer (TLB), which is a cache for address translations, contains an additional copy of the same virtual page number in one of its entries. Our goal is to exploit this redundancy to improve the performance and energy consumption of computing systems that employ page table based address translation. To this end, we introduce SONATA, a microarchitectural modification that proposes to reserve a fraction of registers for offsets and use them as a new register type: Address registers. SONATA stores base addresses belonging to address registers in the TLB. SONATA makes minimal changes to the system and does not change the number of registers or the access mechanism to the overall register file. SONATA offers a reduction in register file's dynamic energy consumption by 6.67%, TLB's energy consumption by 38.56% and ALU energy consumption by 1.86%.