Fault-tolerant adaptive routing algorithm design for network-on-chips

As the technology advances in integrated circuit systems, the number of cores increases and dimensions of transistors are getting smaller. This leaves the relevant structures more susceptible to errors. Designers, who prioritize performance, avoid classical approaches and need more complicated algorithms that can tolerate possible adversities. The concept of the Network-on-Chip (NoC) comes into play, giving flexibility to the circuit in areas such as scalability and delay time. Within the scope of the thesis study, it is aimed to design a routing algorithm by tackling the problems affecting the performance such as congestion and temporary / permanent error in multi-node structures. HARAQ has been evaluated as a premise method with its powerful machine learning mechanism. The identified bogus jam issue has been eliminated in a probabilistic way and the algorithm is strengthened by fault tolerance feature. As a result of the described, congestion-aware and error-tolerant adaptive HAFTA method has been introduced, which is uncommon in similar academic studies. In the experimental phase, some simulations were carried out with widespread traffic models and the success of the designed algorithm was evaluated in terms of the determined criteria.