Design of real time modulator and demodulator using very high speed integrated circuit hardware description language

In this thesis, real-time modulator-demodulators are designed by using Altera DE-0 Nano Board and, improved novel architectures are introduced for BPSK (Binary Phase Shift Keying), QPSK (Quadrate Phase Shift Keying), and MSK (Minimum Shift Keying) modulation techniques. Compared with MUX based structures, improved BPSK and QPSK modulator architectures save ram bit usage by up to 87.5% and use fewer TLE (Total Logic Element) and Registers. This achievement is provided suggesting a new technique to generate carrier signal of improved BPSK and QPSK architectures. Furthermore, three novel modulator architectures are designed for MSK modulation technique in the thesis. In first, I and Q channel signals are generated by using MUX based architectures. In addition to, the resource utilization of the architecture is reduced by performing substitution technique. The second is designed by using symmetrical feature of the I and Q channel signals and it reduces ram bit usage by approximately 75%. The last architecture is completely a novel structure and is referred to as R-F MSK. R-F MSK is designed deriving two novel equations. Additionally, pre-computation technique is used to reduce ram bit usage of R-F MSK. Improved all architectures are run as real-time on FPGA board and modulated signals are showed on oscilloscope.