Design of a cellular neural network emulator and its implementation on an FPGA device

It is well known that technology affect our everyday lives and change them signi?cantlyfrom the beginning of humanity. As the technology grows more rapidly in the last fewdecades, the changes also started to occur more frequently. For example, a few centuriesago, a person could experience at most one signi?cant leap of change in his or her life; buttoday, a senior may have experienced the leaps caused by the inventions of the television,transistors, satellites, computers, cellular phones, other portable electronics, etc.The rapid change of the technology also create trends of new research topics, like imageprocessing, which was nothing more than a television or camera engineers or academicsspecialty just 20 years ago. Furthermore, the processing was limited by preserving, transmitting and receiving images with minimum noise and distortion. With the introduction ofdigital cameras, countless new ideas of image processing emerged, e.g., image enhancement, image compression, automated target recognition and tracking, biometric recognition, etc. There are two main dif?culties in the application of these ideas: (1) new imageprocessing algorithms should be developed and implemented within tight time framesand (2) fast and parallel processors are required to match the computation intensity of thereal?time image processing.On the other hand, a Cellular Neural Network (CNN) is a multi?dimensional signal processing paradigm, whose analog and digital 2?D implementations can be used in imageprocessing. The main advantage of any CNN implementation is that, many image processing algorithms can be implemented on the same structure, solving the ?rst problemmentioned above. On the other hand, analog CNN implementations are known to operate at speeds up to 10 kilo?frames/s for grayscale images with resolutions lower then176 144, which seems to solve the second problem. However, this is not the case forxivhigh?resolution and medium frame?rate images like full?HD 1080p@60 (1920 1080resolution, 60 Hz frame rate), where the performance of the analog implementations dropbelow the real?time limits. Then again, the digital implementations of CNN does not havethe intrinsic parallel connectivity of their analog counterparts, consequently, none of thedigital CNN implementations are reported to operate for full?HD 1080p@60.In this thesis, an improved real?time digital CNN architecture capable of processing full?HD 1080p@60 video images is proposed, described in VHDL and realized on two different FPGA devices. The architecture is designed to have superior properties over itspredecessors. First, the architecture is highly scalable, which is proven by implementingthe same design on a high?end and a low?cost FPGA device. Second, most parts of thestructure are designed to be recon?gurable and ?exible, e.g., the size of the CNN templates, ?xed?point bit?widths of all signals, the number of iterations, etc. Third, mostparameters like template coef?cients, bias, boundary conditions and bypass modes areprogrammable at runtime. The architecture proposed in this thesis is the only CNN implementation reported in the literature that assemble all of these features together.Keywords: cellular neural networks, image processing, ?eld?programmable gate-arrays,real?time systems