Design of low jitter 8 GHz 22-nm SOI-CMOS pll for precision data converters

An ultra-low jitter integer- N PLL is presented as a sampling clock source for precision data converter applications. This design is implemented in 22-nm FDSOI process. A low-noise edge-triggered PFD architecture is proposed. A differential CP with an error amplifier is introduced for a smooth transition of current and achieving high speeds. LC-tank VCO with a low noise LDO is utilized to improve the PSRR and phase noise. TSPC divider with a modulus output selection resulted in improved phase noise with respect to standard DFF-based divider topologies. XO, PFD, and CP are operated at 1 GHz to suppress the in-band noise contribution of the XO, PFD, CP, and divider. Output frequency ranges from 7.1 GHz to 8.4 GHz with a FTR of 17%. PLL has an 89.5° phase margin and 5.46 MHz bandwidth. PLL achieves -130 dBc/Hz phase noise at 1MHz offset from an 8 GHz carrier. The resultant RMS jitter integrated from 12 kHz to 20 MHz is 21.8 fs