FPGA implementation of compressive sensing signal reconstruction

Compressive sensing (CS) is a prominent signal processing method that allows signal acquisition and recovery from fewer samples than the Nyquist- Shannon sampling theory dictates. Two basic conditions to proper recovery of the sub-sampled signals are the sparsity of the signal and the randomness of the sensing mechanism. Applications incorporating real-time signals greatly benefit from the CS as most signals show sparsity in some transform domain. Disadvantage of the CS method is that it requires complex reconstruction algorithms to recover the original signal from the obtained samples. Since the software implementations are not suitable for the practical real-time applications, overcoming this problem makes it necessary to utilize hardware accelerators for the task. In this thesis, a novel hardware architecture that realizes the Orthogonal Matching Pursuit (OMP) algorithm is proposed. The proposed architecture is designed to be scalable and can be adjusted to different problem size depending on the application and the target device. Parallel processing is used to reduce the latency of the design in applicable stages of the algorithm. Implemented hardware is synthesized and verified on an FPGA to evaluate the performance. Experimental results indicate that the proposed design achieves faster reconstruction times than the prior FPGA implementations for the signals that show high sparsity.