FPGA based printed circuit board defect detection with a deep learning algorithm

With the developing industry, the miniaturization of electronic boards and circuit paths, which are the basis of electronics in our lives, complicates PCB (Printed Circuit Board) production and can cause defects on the final product. Defects occurring on the PCB should be checked carefully using equipment such as a magnifying glass due to the size of the electronic cards. This method is time-consuming and prone to mistakes. Failure of detection of defects may cause the device to fail in a short time and its performance to remain at low levels, which will cause a decrease in product/brand demand by victimizing the user. As a solution, including systems working with deep learning models, used in object detection, in production or post-production stages can be suggested. These systems must detect defects on PCBs with high accuracy and speed. FPGAs (Field Programmable Gate Array) provide a more suitable environment for real-time systems, with their parallel processing capability, flexibility in design and re-programmability, compared to CPU (Central Processing Unit), GPU (Graphical Processing Unit) and hybrid structures (SoC - System on Chip) which are generally used in these systems. In this thesis, an FPGA-based architecture is proposed that detects defects, which occur after PCB production, with the help of a deep learning model. The open-source dataset used in this study contains 9666 images and 7 different defect classes. In the thesis, one of the upper versions of the YOLOv8 model, the YOLOv11 version, is used as the deep learning model, which is the latest version used in this with FPGA field so far. To understand the performance differences, YOLOv8 and YOLOv11 models are trained under the same conditions and their performances are compared. In the parameter-performance relationship, the YOLOv11n model, which occupies less space in embedded systems and achieving 98,4% mAP50 (mean average precision for IoU - Intersection over Union – at threshold 0,50) performance in the final training, is examined by creating only RTL (Register Transfer Language) based FPGA architecture without GPU or CPU support. Within the observations in examinations, the overall mAP50 value is preserved at 97,86% with the inference speed is 34,9386306ms. The fact of the preservation of detection capability with a very small amount of loss proves the RTL implementation of YOLOv11n model is possible. The results in this thesis shed light on the systems contains FPGA as processing power can be used instead of CPU, GPU and hybrid structures in real-time systems.