Designs of cellular neural network and chaotic circuit based random number generator

In this thesis, the architecture, types and features of Random Number Generator (RNG) used in cryptographic applications have been examined in detail, real time random number/bit generation has been implemented on Field Programmable Gate Array (FPGA) board by exercising chaos based RNG designs. Moreover, some of chaotic systems in the literature have been examined in detail and hardware based simulations of systems have been realized in Xilinx System Generator (XSG) platform. In this thesis study, three different RNG designs were proposed. After the hardware based realizations of the designs in XSG platform, RNG designs have been coded by using Verilog Hardware Description Language (HDL) through the Xilinx ISE FPGA Editor interface program. The statistical randomness of bit streams derived from the RNG designs were validated with National Institute of Standards and Technology (NIST) 800.22 test suite. Furthermore, the degree of non-periodicity of the bit streams has been determined by adopting scale index algorithm. In the thesis, the first proposed RNG design is a simulation study. In the design, a chaotic system with three state variables and Trivium encryption algorithm have been made use of as entropy source and post processor, respectively. By examining hardware based simulation of the design in XSG platform, the generated bit stream has been tested statistically. In the second proposed RNG design, making use of three cell autonomous Cellular Neural Network (CNN) model that represents chaotic behavior as entropy source and Trivium encryption algorithm as post processor, bit stream generation has been realized for three different scenarios. Thus, the design performed random bit generation with an output bit rate of 2.015 Mbps. In the third proposed RNG design, Memristive chaotic CNN model and logistic map were utilized as entropy source. The random bit generation has been examined by sampling and digitizing the output of two chaotic systems then applying to XOR post processor. As a result of performed design, it is demonstrated that random bit generation was achieved with an output bit rate of 125 kbps and very low FPGA resource utilization.